Field of the Invention
The invention relates in general to a delay locked loop, and more particularly to a multiplying delay locked loop.
Description of the Related Art
A timing device is commonly applied in electronic devices and systems to generate a clock and to allow various elements to operate synchronously. A multiplying delay locked loop (MDLL) is one of the above conventional timing device, as exemplified by an MDLL 100 in FIG. 1. FIG. 2 shows a timing diagram of signals in the MDLL 100. In the MDLL 100, every rising edge of a reference clock signal rclk enters a delay line via a multiplexer 110. After a rising edge of the reference clock signal rclk enters the delay line 108 via the multiplexer 110, a selection signal sel switches to select an output signal bclk of the delay line 108 as an input signal iclk of the delay line 108. At this point, a ring oscillator is formed. The ring oscillator generates clock signals having a period T. After (M−1) clock signal periods, an integer divider 106 (e.g., having a divisor M equal to 8 in the example in FIG. 2) generates a last signal last, in which a pulse represents a last period (the Mth period) of the output signal bclk. The last signal last may be regarded as an indication signal that indicates the time point at which the Mth clock period appears. After the rising edge of the last signal last, a logic circuit 104 causes the selection signal sel to generate a pulse to control the multiplexer 110, allowing the next rising edge of the reference clock signal rclk to enter and serve as the input signal iclk of the delay line 108. Meanwhile, the delay adjuster 102 compares this rising edge with the rising edge of the output signal bclk to determine a phase difference dt between the two, and generates a control voltage VCNTL to adjust the delay time from the input signal iclk to the output signal bclk in the delay line 108. The goal of the entire circuit operation is to render the phase difference dt to be approximately 0 to lock the phase. When the phase is locked, a clock period of each reference clock signal rclk is equal to M clock periods of the output signal bclk, and the Mth rising edge of the output signal bclk is approximately aligned with or appears at about the same time as one rising edge of the reference clock signal rclk.
The MDLL 100 provides numerous advantages. For example, each time the rising edge of the reference clock signal rclk appears, the MDLL 100 may reset the phase difference dt between the output signal bclk and the reference clock signal rclk to zero. Thus, the MDLL 100 prevents an effect of accumulated phase difference generated by a phase locked loop that commonly serves as a timing device. Further, as only one single delay line 108 is utilized to generate the output signal bclk, issues of device mismatch caused by process factors in the delay line 108 do not affect the waveform of the output signal bclk. Moreover, the divisor M in the integer divider 106 may be configurable to generate various output signal bclk having different ratios to the clock period of the reference clock signal rclk.
However, the MDLL 100 suffers from certain issues, and needs to be carefully designed. For example, in general, the reference clock signal rclk needs to be extremely clean and cannot tolerate any drastic jitter, or else the jitter may be directly reflected upon the output signal bclk. Further, with a small design mistake, the jitter in the reference clock signal rclk may lead to disturbances in the MDLL 100 to incur wrongful results.